1. Field of the Invention
The present invention relates in general to bit synchronizers, and more particularly to a bit synchronizer for non-return to zero (NRZ) data wherein a loop gain of a phase locked loop (PLL) in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage controlled oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse even in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional bit synchronizer. In this drawing, the conventional bit synchronizer is shown to comprise a phase comparator (PC) 11, a low pass filter (or an integrator) 12 and a voltage control led oscillator (VCO) 13.
In the conventional bit synchronizer, as shown in FIG. 1, an output of the phase comparator (referred to hereinafter as "PC") 11 is connected directly to an input of the low pass filter (or the integrator) 12. Examples of this form of bit synchronizer are described in U.S. Pat. No. 4,400,667, Belkin, U.K. Patent No. 8039874 and U.S. Pat. No. 4,422,276, Summers, and U.S. Pat. No. 4,535,459, Hogge. It is also common that a loop gain of a phase locked loop (PLL) is varied sensitively to a bit pattern of the received NRZ data (probability that NRZ data transitions will occur) since the output of the PC for bit synchronization is varied as a function of the number of the NRZ data transitions (a gain of the PC is varied as a function of a density of the NRZ data transitions). One example of this form of bit synchronizer is shown in D. L. Duttweiler, "The Jitter Performance of Phase-Locked Loops Extracting Timing from Baseband Data Waveforms", The Bell System Technical Journal, Jan 1976. For this reason, making the loop gain of the PLL circuit larger causes the unstable operation of the bit synchronizer when a large number of the data transitions occur. Also, making the loop gain of the PLL circuit smaller causes the unstable operation of the bit synchronizer when a small number of the data transitions occur.
Also in the conventional bit synchronizer, the low pass filter or the integrator 12 of the PLL detects a magnitude of a low frequency component containing a DC component from the output pulse from the PC 11. The detected magnitude from the low pass filter or the integrator 12 is then applied to the voltage controlled oscillator (referred to hereinafter as "VCO") 13. In the case where the output pulse from the PC 11 is of a narrow width (the bit rate of the data is high), the low frequency component is of such a very small magnitude not as to detect it. This results in the unstable operation of the PLL circuit. Examples of this form of bit synchronizer are described in U.S. Pat. No. 4,400,667, Belkin, U.K. Patent No. 8039874 and U.S. Pat. No. 4,422,276, Summers, and U.S. Pat. No. 4,535,459, Hogge.
In order to solve the above problems, there have recently been proposed several bit synchronizers. In one of the proposed bit synchronizers, there is provided a separate PLL for monitoring the VCO frequency, in addition to the bit synchronizing PLL for data recovery. The bit synchronization is performed by separating the frequency and the phase from each other. One example of this form of bit synchronizer is described in U.S. Pat. No. 4,787,079, R. P. Rizzo. In another bit synchronizer, the PLL comprises both the low pass filter and the integrator which controls the VCO simultaneously to enhance the bit synchronizing performance. One example of this form of bit synchronizer is described in Japanese Patent No. Sho 53-153494 and U.S. Pat. No. 4,942,370, T. Shigemori. With the above proposed bit synchronizers, however, the above-mentioned conventional problems cannot basically be solved in that the output of the PC or a frequency comparator (FC) is connected directly to the input of the low pass filter or the integrator 12.